1. Field of the Invention
The present invention relates, in general, to a synchronization circuit and, more particularly, to a circuit aligning the pulses of an input signal with those of a clock.
This application is a counterpart of Japanese patent application, Serial Number 378061/2001, filed Dec. 12, 2001, the subject matter of which is incorporated herein by reference.
2. Description of Related Art
When a signal is transferred between equipment which are located with a long distance each other, there the following situations occur occasionally. One is that duty rate of the pulses of the input signal is smaller than those of the clock signal. The other is that duty rate of the pulses of the input are not constant. Another is that the speed of the input signal is unstable because the pulses are not comprised at even intervals. To solve the above problem, the input signal is sampled using the clock signal of which frequency is higher than of the input signal. However, when the input signal has high frequency as the clock signal, there are times when a part of the pulse of the input signal is lack at sampling. The conventional synchronization circuit, Japanese Patent Application Laid Open No. 11-331137 (corresponding to European patent application publication No. EP 0942533A2), provides the circuit for solving the above problem.
However, the conventional circuit requires connecting with two flip-flops in series which are provided a common clock signal, in order to avoid a metastable state. The metastable state occurs in a state that the clock raises or falls before passing a setup time or hold time for the data of the flip-flop. Therefore, the conventional circuit requires four flip-flops which are connected in series.
According to one aspect of the present invention, there is provided a synchronous circuit comprising a first flip-flop which has a first clock input terminal inputting an input signal, a first output terminal outputting a first output signal based on the input signal, a second output terminal outputting a second output signal based on the input signal and a first data input terminal inputting the second output signal, a second flip-flop which has a second clock input terminal inputting a clock signal, a reset terminal inputting a reset signal, a third output terminal outputting a third output signal based on the clock signal and the reset signal, a fourth output terminal outputting a fourth output signal based on the clock signal and the reset signal and a second data input terminal inputting the fourth output signal, third flip-flop which has a third clock input terminal inputting the third output signal of which voltage level is reversed, a fifth output terminal outputting a fifth output signal based on the reversed third output signal, a sixth output terminal outputting a sixth output signal based on the reversed third output signal and a third data input terminal inputting the sixth output signal, and a logical circuit which generates the reset signal using the first output signal and the fifth output signal.
The novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.